1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and, more particularly, to an integrated circuit and an operation method thereof for detecting an operation state of an internal circuit by sensing variation in a current amount flowing on a signal transmission line coupled to the internal circuit.
2. Description of the Related Art
Demand for a semiconductor device that performs a program operation and an erase operation without a refresh operation for rewriting data with a predetermined period has increased. A high integration technology for a memory device having a high-capacity memory for storing large amounts of data has developed. Herein, the program operation represents a write operation for writing data on a memory cell, and the erase operation represents an erase operation for erasing data stored on the memory cell.
Recently, a NAND-type flash memory device having a string composed of a plurality of memory cells, which are coupled in series, has developed. The NAND-type flash memory device sequentially reads information unlike a NOR-type flash memory device. The program operation and the erase operation of the NAND-type flash memory device are performed by injecting or ejecting electrons into a floating gate using an F-N tunneling manner and controlling a threshold voltage of the memory cells.
FIG. 1 is a block diagram illustrating a conventional flash memory device.
As illustrated in FIG. 1, the conventional flash memory device includes a memory cell array 10 having a plurality of memory cells and a page buffer 20.
The page buffer 20 includes a bit line selection unit 21, a precharge unit 22, and a register 23. The bit line selection unit 21 is coupled between a sensing node S0 and bit lines BLe and BLo. The precharge unit 22 is coupled to the sensing node S0. The register 23 is coupled between the sensing node S0 and an input/output terminal YA. The register 23 includes a latch 24 for temporally storing data.
The page buffer 20 transmits a program data to one of the bit lines BLe and BLo through the sensing node S0 that is precharged by the precharge unit 22 during a program operation, and stores data transmitted through one of the bit lines BLe and BLo in the latch 24 of the register 23 through the sensing node S0, which is precharged by the precharge unit 22, during a read operation. The sensing node S0 is precharged by the precharge unit 22 during various operation of a flash memory device such as a copy-back operation, a verification operation, the program operation, and the read operation.
More specifically, during the read operation for checking a program state or an erase state, cell current flowing on a memory cell to be read is sensed through the bit lines BLe and BLo, and a cell state of the memory cell is determined based on a sensed result. For example, if the memory cell to be read is the program state, a voltage level of the bit lines BLe and BLo maintains a level set by a precharge operation since the cell current does not flow. If the memory cell to be read is the erase state, a voltage level of the bit lines BLe and BLo is lowered than a level, which is set by the precharge operation, since the cell current flows. The cell state is checked by detecting such a state through the sensing node S0.
However, as the integration of a flash memory device is increased and power used in the flash memory device becomes lower, a cell current of a memory cell may be reduced. Thus, during the read operation for checking the cell state, a variation width of the voltage level of the bit lines BLe and BLo may be reduced, and a reading margin may be reduced. That is, during the read operation, a time for acquiring a sufficient variation width of the voltage level of the bit lines BLe and BLo may be increased, and an operation speed of devices may be reduced.